Computer Organization
Q101.
Which of the following statements about synchronous and asynchronous I/O is NOT true?Q103.
Which of the following DMA transfer modes and interrupt handling mechanisms will enable the highest I/O band-width?Q105.
A device with data transfer rate 10 KB/sec is connected to a CPU. Data is transferred byte-wise. Let the interrupt overhead be 4 \musec. The byte transfer time between the device interfaces register and CPU or memory is negligible. What is the minimum performance gain of operating the device under interrupt mode over operating it under program-controlled mode?Q106.
Normally user programs are prevented from handling I/O directly by I/O instructions in them. For CPUs having explicit I/O instructions, such I/O protection is ensured by having the I/O instructions privileged. In a CPU with memory mapped I/O, there is no explicit I/O instruction. Which one of the following is true for a CPU with memory mapped I/O?Q108.
A keyboard connected to a computer is used at a rate of 1 keystroke per second. The computer system polls the keyboard every 10 ms (milli seconds) to check for a keystroke and consumes 100 \mu s (micro seconds) for each poll. If it is determined after polling that a key has been pressed, the system consumes an additional 200 \mu s to process the keystroke. Let T_1 denote the fraction of a second spent in polling and processing a keystroke. In an alternative implementation, the system uses interrupts instead of polling. An interrupt is raised for every keystroke. It takes a total of 1 ms for servicing an interrupt and processing a keystroke. Let T_2 denote the fraction of a second spent in servicing the interrupt and processing a keystroke. The ratio \frac{T_1}{T_2} is ______ . (Rounded off to one decimal place)Q109.
In 8085 microprocessor, the ISR for handling trap interrupt is at which location?Q110.
The correct matching for the following pairs is:\begin{array}{ll} \text{(A) DMA I/O} & \text{(1) High speed RAM} \\ \text{(B) Cache} & \text{(2) Disk} \\ \text{(C) Interrupt I/O} & \text{(3) Printer} \\ \text{(D) Condition Code Register} & \text{(4) ALU} \\ \end{array}